Generally, the high integration of a DRAM has been achieved through the development of fabrication equipment and processing technology of semiconductor devices, designing techniques, memory cell structure, etc.
However, there have been many problems in developing highly integrated memory devices due to the physically imposed limitations consisting in the semiconductor fabrication equipment and semiconductor device itself.
For example, in order to achieve a highly integrated memory device the area for the storage capacitor should be as small as possible. However, in a conventional memory structure where a storage capacitor and a switching transistor are arranged horizontally, makes it substantially impossible to reduce the areas for the capacitor and transistor, due to the physically imposed limitations, but also requires a precision configuration/layout by semiconductor fabrication equipment, in order to achieve a highly integrated memory device. Furthermore, the processing technology such as a precision configuration/layout technique is itself very difficult to develop due to inherent technical limitations.
FIG. 1a illustrates a cross sectional view of the structure of a conventional DRAM, wherein a switching transistor and storage capacitor are horizontally arranged, and FIG. 1b is an equivalent circuit of FIG. 1a. Referring to FIG. 1a, 40 and 41 respectively represent the drain and source (or source and drain) of the transistor Q shown in FIG. 1b that are formed on silicon substrate 10. The reference numeral 60 represents the contact between bit line B1 and the diffusion region 40 forming the drain or source. The reference numeral 20 represents an insulating layer for isolating the bit line B1 from word line W13. The word lines W10, W11, . . . and electrode PE are made of polysilicon, and the bit line B1 are made of aluminum.
In an N-channel MOSFET (metal-oxide-semiconductor field effect transistor), the storage capacitor Co is formed between channel 50 and the electrode PE applied is with a high voltage. In this case, if a pulse voltage is applied to the word line W10, the transistor Q, comprising the drain 40 and source 41 connected between the word line W10 and bit line B1, conducts current, so that the voltage stored in the storage capacitor Co is read out and divided by the bit line B1 and the capacitance of the storage capacitor Co.
More specifically, when the word line W10 is applied with a voltage in order to write data into the conventional DRAM cell, the transistor Q conducts current by the voltage applied to its gate, so that the data loaded in the bit line B1 (i.e., voltage of "1" or "0" level) is stored through the conducting transistor Q into the storage capacitor Co.
On the other hand, one electrode of the capacitor Co is the plate electrode applied with a constant reference voltage, while the other electrode, which is a storage electrode, maintains the voltage stored in the capacitor Co. The voltage of the bit line B1 may be sufficiently written into the capacitor, provided that the voltage of the word line W10 exceeds than the voltage of the bit line B1 by a threshold voltage.
In order to read out the data stored in the capacitor, the bit line B1 is precharged with the reference voltage, and the pulse voltage is applied to the word line W10, so that the transistor Q conducts current, so as to deliver the data stored in the capacitor to the bit line. At this time, the bit line undergoes a small voltage variation that is amplified to readable data.
A typical stacked type conventional DRAM is specifically illustrate in FIG. 1c, wherein the reference numeral 10 represents silicon substrate 10, 40 and 41 respectively the drain and source (or source and drain) of the transistor Q as shown in FIG. 1a, and B1 and W10 respectively the bit and word lines. The storage capacitor consists of plate electrode PE, storage electrode SE, and dielectric layer DE. This kind of conventional DRAM is disclosed in U.S. Pat. Nos. 4,044,340 issued on Aug. 23, 1977, 3,876,992, 3,979,734, 4,190,466, etc.
In such conventional DRAMs, the areas for the switching transistor and capacitor are large, and the bit line B1 and the plate electrode of the capacitor are separated from each other, so that the process for fabricating contacts, etc. of the memory is complicated, thus making it impossible to achieve a highly integrated memory. In addition, since the transfer transistor consists of a MOS transistor that has a lower current drive capability than a bipolar transistor, its operating speed is somewhat slower.